1. Field of the Invention
The present invention relates to the manufacturing of a semiconductor wafer covered with a plate of glass and particularly to the manufacturing of a wafer comprising CMOS imagers.
2. Description of the Related Art
Imagers produced according to the CMOS (“Complementary Metal Oxide Semiconductor”) technology are the subject of an increasing number of applications due to their low cost price in comparison with CCD (“Charge Coupled Device”) imagers. Such CMOS imagers were initially used to produce low resolution image sensors of mediocre quality (for example web cameras). Today, after major investment in research and development, CMOS imagers can compete with CCD imagers. One embodiment of the present invention is in line with an effort to develop and improve this imager technology aiming to reduce the cost prices with at least equal image quality.
FIG. 1 represents an example of a module for capturing images and/or video using a CMOS imager, intended for example to be mounted into a portable device such as a mobile telephone, a camera or a video camera. The module 1 comprises a frame 2, an optical set 3, lenses 4 fitted into the block 3, an optical filter 5 and a base 6. A semiconductor chip 100 integrating a CMOS imager 10, is disposed on the base 6 and receives the light passing through the lenses 4 and the filter 5. The filter 5 is generally an infrared filter (consumer applications) but can also be a specific filter for industrial applications needing to capture images in a certain frequency range or to reject certain frequency ranges.
The CMOS imager 10 comprises photosites each forming one pixel (not visible in FIG. 1). Each pixel comprises a photodiode and a control and interconnection circuit of the photodiode. The pixels are arranged as an array and a mosaic of red, green and blue filters is distributed over the pixel array, generally according to the Bayer architecture.
FIG. 2 is a schematic cross-section of the chip 100 and of the imager 10 in a region corresponding to three pixels PIX1, PIX2, PIX3. A semiconductor substrate 15 into which the imager 10 is implanted, and a glass chip 20 fixed onto the imager through a layer of glue 19 can be distinguished.
Going from bottom to top, the imager 10 comprises layers 10-1, 10-2, 10-3, 10-4, 10-5 and microlenses L0-1, L0-2, and L0-3. The layer 10-1 represents the active part of the imager and comprises photodiodes 14-1, 14-2, 14-3 and their associated control and interconnection circuits (not detailed). The layer 10-2 is a dielectric material that entirely covers the substrate 15. The layer 10-3 is a passivating layer deposited on the imager at the end of the manufacturing process. The layer 10-4 is formed by colored resins and comprises red, green or blue areas R, G, B forming the above-mentioned primary color filters, with one color filter per pixel. The layer 10-5 is an intermediate layer of resin forming a base for the microlenses L0 and providing good flatness (“planarization” layer). The microlenses L0 are arranged in a “MLA” (Microlens Array) with one microlens per pixel, and are covered with the layer of glue 19 and with the glass chip 20.
Steps of a classic method of manufacturing the imager chip 100 are represented in FIGS. 3A to 3E. The method first of all comprises the collective manufacturing of a plurality of imagers 10 on a silicon wafer 15′, as represented in FIG. 3A. In the step shown in FIG. 3B, a glass plate 20′ is fixed onto the front face of the wafer 15′ through a layer of glue 19′ covering the entire wafer, the glue comprising for example epoxy, urethane, silicon, etc. In the step in FIG. 3C, the wafer 15′ is turned over and is put on a base (not represented) to treat its rear face. This treatment on the rear face comprises at least one step of thinning the wafer, a step of etching and a step of sawing the wafer to obtain a plurality of imager chips like the chip 100.
The step of thinning, represented in FIG. 3D, is generally performed by backlapping, and comprises the grinding and the polishing of the rear face. The thickness of the wafer, initially in the order of a few hundred micrometers is in the order of a few tens or one hundred micrometers at the end of the process.
The step of etching, represented in FIG. 3E, enables grooves 25 to be obtained on the rear face of the wafer. These grooves can be provided for various reasons, for example to facilitate the subsequent cutting of the wafer or to produce contacts on the rear face. The grooves 25 are generally produced by chemical etching or plasma etching.
A micro-module for capturing images as represented in FIG. 1 has the disadvantage of having a relatively complex structure and of requiring considerable assembly time, which increases its cost price.
In particular, the filter 5 is an additional component of a high cost price and requires a dedicated manufacturing line, then steps of storing, handling and assembling.